The overall array architecture for a typical virtual ground array based flash memory device includes a virtual ground array accessed by a set of row decoders and a set of column decoders/multiplexors. The virtual ground array contains information stored in individual memory elements. The row/word-line decoders are used to access specific memory rows within each memory block and the column decoder/multiplexor provides the input and output circuitry for each memory element.
The architecture of a virtual ground array comprises both individual memory elements and select gates. The memory elements are embodied in non-volatile transistors that may be programmed to a logic state of 0, 1, or other states depending on the particular type of transistor and programming used. The select gates are embodied in normal MOSFETs. Selectable word lines address both the control gates of the transistors that comprise the individual memory elements and select gates in the virtual ground array. Sets of memory elements are connected in series along each word line. The select gates are connected in pairs that are coupled to alternate select gate address lines. The pairs of select gates are connected with pairs of memory elements and a global bitline. Multiplexors control the columns that are connected to the external circuitry, such as the sensing circuitry and data-in path. The multiplexors are controlled by a set of column address decoders. Thus, the decoders and multiplexors regulate the flow of data into and out of the virtual ground array.
Variations of the threshold voltage of the individual memory elements within the virtual memory array occur as a result of continual erasing and programming over time of the memory device. After an erase/program operation on memory elements in the array it is necessary to verify that the memory elements have been erased or programmed to the correct level. The levels may be determined by using a safe and accurate sensing scheme that senses from the source rather than the drain side of the virtual ground array. Using the drain side has a number of disadvantages. The main disadvantage of drain side sensing is that all the other bitlines connected with memory elements on the drain side not being sensed must be precharged to the drain voltage or higher before the sensing routine commences. Precharging the bitlines, in this case, wastes both time and power. Time is necessary to initiate, perform, and verify the precharging sequence when sensing from the drain side. Excess power is consumed in each of the precharge steps as well, for example decreasing battery lifetime for any portable electronics unit using the virtual ground array. In addition, sensing from the drain side leads to larger leakage currents and more thus error. Further, once it has been determined that the levels have deviated significantly from previous values necessary for normal operation, the window of operating voltages must be altered to decrease any errors obtained during normal operations due to the change.